80 Core Processor !!!???

Intel has announced a research chip that contains 80 (yes, eighty!!) cores. Each is a dual floating point execution unit. That's a record of maximum integration! This achieves a performance of 1 teraflops at 3.16 Ghz. That's a supercomputer performance that can make supercomputer on a desk possible when commercially available.


All that performance at an energy expense of 62 watts only, lower than some of the PC chips today! As I have mentioned couple of times in my past posts, this is what's going to happen. Ever more performance at as low a consumption as is possible. Otherwise the way the need for more performance, whether through such high performance devices or a multitude of servers, increases the energy consumption and corresponding cooling requirements will become unmanageable.

Only thing comparable has been a supercomputer built by Intel with 10,000 Pentium chips that reached teraflop performance yet consumed 500 KW of power! This was a supercomputer housed in Sandia National Labs of USA. Mind boggles just to think of possibilities when such power would be available for personal use! Some of the applications being talked about are real time speech recognition, multimedia data mining, photo-realistic game etc. That would/could lead to immediate speech based interaction with the computer like the HAL of 2001 A Space Odyssey! Digging out a photo of some one with a smile on his face in contrast to his frowning! Photo realism particularly in real time animation would add a totally different dimension to gaming experience!

With several processors running together, system bus saturates very soon. Caches help but even then limits are reached very soon, as numbers increase. Memory interface speeds, data management between these cores, keeping them current are some of the problem areas. Particularly the interface speeds possible on this system bus.

Intels' stated aim is to research these areas with a chip like this. Innovations generated in the project as per Intel are as follows,

1. Rapid design – The tiled–design approach allows designers to use smaller cores that can easily be repeated across the chip. A single–core chip of this size (100 million transistors) would take roughly twice as long and twice as many people to design.
2. Network on a chip – In addition to the compute element, each core contains a 5–port messaging passing router. These are connected in a 2D mesh network that implement message–passing. This mesh interconnect scheme could prove much more scalable than today’s multi–core chip interconnects, allowing for better communications between the cores and delivering more processor performance.
3. Fine–grain power management – The individual compute engines and data routers in each core can be activated or put to sleep based on the performance required by the application a person is running. In addition, new circuit techniques give the chip world–class power efficiency—1 teraflops requires only 62W, comparable to desktop processors sold today.
4. And other innovations – Such as sleep transistors, mesochronous clocking, and clock gating.

GIS/GPS Really, Truly Mainstream Now!!

Time, Nov 20 issue, Asia edition features 3 of the most portable and affordable of GPS and combination devices as "Gift of the year". The three devices are Delphi NAV200, Mio H610 digiWalker and Garmin StreetPilot c550. All three are really truly portable, actually hand-held sized. Prices range from about $300 to $750 or so. Location/navigation has become ready for mass use. These can be used for street walks as well as for driving guidance. They come with preloaded maps, cute user interfaces and has added functionality such s MP3 player, phone, PDA etc.

As these are based on quite powerful processors additional functionality become easy. Could be flight directory, weather, traffic update and so on. I can imagine a time very soon when instead of a Lonley Planet country guide, tourists carrying one such device. The device would be multimedia capable and provide all the background information these guides provide!

FSB capability on Multi Core Processors

One recent processor variation of the quad core variety came out earlier than predicted. That probably is the way Intel wants to fight AMD, churning out these processors at a fast and furious pace! Lot of products have already adopted the processors. We faster performance than the dual cores processors of course.

Is it double the performance? It never could be. However how much flattening does happen will decide how many cores can one put together. If the performance starts saturating at 4 cores, will it make sense to scale up to 8!! One of major reason for the performance knee is the saturation of the system bus or the main bus to system memory.

That this is on the minds of the designers is evident from the specs for the FSB or the front side bus or the bus to the main memory has been enhanced.

Quad Core Processors Are Here Already!

The transition from 2 core to 4 cores per processors cam really fast! Not only the chips are available, real products has started becoming commercially available. Looks like this strategy must have been in process for quite some time now. Intel had started deemphasizing higher clock speeds as the solution for higher performance for quite some time now. In between came hyperthreading architecture, then the multi cores!

Chip performance has jumped significantly with each of these two generations. To harness this enhancement in raw power there's quite a few things that are needed. Very first thing would be the system bus just outside the chip boundary or the FSB in a desktop. Then of course OS needs to be able to schedule processes optimally. Load balancing and hence scaling will depend a lot on how fine grained processes are or can be made. Ideal situation is of course when all 4 cores are busy all the time, except the task switching times.

So it is safe to assume that by the time all these factors have been fully utilized it'll be another couple of years. Hopefully some more multi core upgrades can be expected by then. However, performance gain has to be approaching the diminishing return part of the curve. I had speculated on some factors that would cause this to happen in an earlier post.